1. Field of the Invention
The present invention relates to a wafer and a test technique thereof. More particularly, the present invention relates to a wafer and a test technique thereof capable of shortening test time.
2. Description of Related Art
When a chip is in wafer stage, it is necessary to perform a chip probe (CP) test on each chip in the wafer, so as to filter chips with defects, and to reduce the fabricating cost. Common CP test includes two stages, namely a high voltage stress (HVS) test and a function test. For the HVS test, an operating voltage exceeding an operating voltage specified by an instruction (or referred to as specification) of the chip is provided to the chip in a short time, and simultaneously some basic signals required by the chip are provided, such that the chip operates under an over-high operating voltage. When the chip operates under the over-high operating voltage, the defects of the chip can be further deteriorated in a short time. Therefore, the function test perform subsequently can be used to further inspect the chips.
Generally speaking, the chips on the wafer each has a great number of input ends and output ends (may be totally hundreds of pads), so when the CP test is performed, it is necessary for a wafer test device to have probes with a corresponding quantity to perform the CP test. However, the probes of the wafer test device are quite expensive, and in consideration of the cost, it is impossible to greatly increase the probes of the wafer test device, so usually the wafer test device can only perform the CP test on one chip on the wafer. Detailed description on various steps of the wafer test is provided below together with the drawings.
FIG. 1 is an architecture view of a conventional wafer test system. Referring to FIG. 1, a wafer to be tested 100 has a plurality of chips (indicated by chips 111 and 112). When a test station 150 intends to perform the CP test on the chip 111 on the wafer 100, firstly, the test station 150 controls a mechanical arm (not shown) to move a substrate 130, thereby driving a probe group 140 to contact pads of the chip 111. Next, the test station 150 provides a power source higher than a rated operating voltage and basic operating signals to the chip 111 through the probe group 140, thereby performing the HVS test for approximately 0.3-0.6 seconds. If the chip 111 has defects, the HVS test may deteriorate the defects of the chip 111, otherwise the HVS test may not affect the function of the chip 111.
After the HVS test on the chip 111 is finished, the test station 150 performs the function test on the chip 111 for approximately 0.3 seconds. During the function test, the test station 150 again provides some basic operating signals and a rated power source to the input ends of the chip 111 through the probe group 140, and reads output signals of the chip 111 through the probe group 140. Therefore, the test station 150 can determine whether the function of the chi 111 is normal or not. In this manner, the CP test of the chip 111 is finished. Next, the test station 150 further controls the mechanical arm to move the probe group 140, so as to make the probe group 140 contact pads of a next chip (chip 112), thereby performing the CP test on the chip 112. Similarly, the CP test is performed on each chip in the wafer 100, and it is not described here.
Suppose that the wafer 100 has 1500 chips, the HVS test for a single chip takes 0.3 seconds and the function test for a single chip takes 0.3 seconds. The time cost by the CP test of the total 1500 chips needs 1500*(0.3+0.3)=900 seconds. If the HVS test for a single chip takes 0.6 seconds, the time cost by the CP test for the total 1500 chips needs 1500*(0.6+0.3)=1350 seconds. It is said that time is money. If it is possible to shorten the time cost by the CP test, the test efficiency of the wafer can be greatly improved, and the cost of the CP test can also be reduced.